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? nec corporation 1991 data sheet mos integrated circuit m pd75p036 4-bit single-chip microcontroller description the m pd75p036 is a 4-bit signgle-chip microcontroller that replaced the m pd75028's on-chip rom with one-time prom or eprom. because this device can operate at the same supply voltage as its mask version, it is suited for preproduction in development stage or small-scale production. the one-time prom version is programmable only once and is useful for small-scale production of many different products and time-to-market of a new product. the eprom version is programmable, erasable, and reprogrammable, and is suited for the evaluation of application systems. detailed functions are described in the followig user's manual. be sure to read it for designing. m pd75028 user's manual: ieu-1280 features ? m pd75028 compatible ? at full production, the m pd75p036 can be replaced with the m pd75028 which incorporates mask rom ? memory capacity ? program memory (prom): 16256 x 8 bits ? data memory (ram): 1024 x 4 bits ? internal pull-up resistors can be specified by software: ports 0-3, 6-8 ? internal pull-down resistors can be specified by software: port 9 ? open-drain input/output: ports 4, 5, 10 ? can operate at low voltage: v dd = 2.7 to 6.0 v ordering information part number package internal rom quality grade m pd75p036cw 64-pin plastic shrink dip (750 mils) one-time prom standard m pd75p036gc-ab8 64-pin plastic qfp (14 x 14 mm) one-time prom standard m pd75p036kg 64-pin ceramic wqfn eprom not applicable caution internal pull-up/pull-down resistors cannot be specified by mask option as for this device. please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on e devices and its recommended applications. h h the reliability of the eprom version, m pd75p036kg, is not guaranteed when used in mass-produced application sets. please use this device only experimentally or for evaluation during trial manufacture. the function common to the one-time prom and eprom versions is referred to as prom throughout this document. the information in this document is subject to change without notice. the mark h shows revised points. document no. u10051ej3v0ds00 (3rd edition) (previous no. ic-2967 date published september 1995 p printed in japan
m pd75p036 2 pin configurations (top view) ? 64-pin plastic shrink dip (750 mils) ? 64-pin plastic qfp (14 x 14 mm) ? 64-pin ceramic wqfn sb1/si/p03 sb0/so/p02 sck/p01 int4/p00 buz/p23 pcl/p22 ppo/p21 pto0/p20 mat/p103 maz/p102 mai/p101 mar/p100 reset x1 x2 v pp xt1 xt2 v dd av dd av ref+ av ref- an7 an6 an5 an4 an3/p113 an2/p112 an1/p111 an0/p110 av ss tio/p13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v ss p30/md0 p31/md1 p32/md2 p33/md3 p40 p41 p42 p43 p50 p51 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p80 p81 p82 p83 p90 p91 p92 p93 p10/int0 p11/int1 p12/int2 p43 p42 p41 p40 md3/p33 md2/p32 md1/p31 sb1/si/p03 sb0/so/p02 sck/p01 int4/p00 buz/p23 pcl/p22 ppo/p21 v ss md0/p30 32 31 30 29 28 27 26 25 24 23 22 21 20 p90 p91 p92 p93 p10/int0 p11/int1 p12/int2 an0/p110 an1/p111 an2/p112 an3/p113 an4 an5 an6 av ss ti0/p13 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p71/kr5 p72/kr6 p73/kr7 p80 p81 p82 p83 p70/kr4 p63/kr3 pto0/p20 mat/p103 maz/p102 mai/p101 mar/p100 reset x1 xt1 xt2 v dd av dd av ref+ av ref- an7 v pp x2 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 52 53 54 55 56 57 58 59 60 61 62 63 64 p52 p53 p60/kr0 p61/kr1 pd75p036cw m pd75p036gc-ab8 m pd75p036kg m
m pd75p036 3 pin identification p00-p03 : port 0 int0, int1, int4 : external vectored interrupt p10-p13 : port 1 int2 : external test input p20-p23 : port 2 x1, x2 : main system clock oscillation p30-p33 : port 3 xt1, xt2 : subsystem clock oscillation p40-p43 : port 4 mar : reference integration p50-p53 : port 5 control p60-p63 : port 6 mai : integration control p70-p73 : port 7 maz : autozero control p80-p83 : port 8 mat : external comparate p90-p93 : port 9 timing input p100-p103 : port 10 ppo : programmable pulse output p110-p113 : port 11 mft timer mode kr0-kr7 : key return an0-an7 : analog input sck : serial clock av ref+ : analog reference (+) si : serial input ab refC : analog reference (C) so : serial output av dd : analog v dd sb0, sb1 : serial bus av ss : analog v ss reset : reset input v dd : positive power supply ti0 : timer input v ss : ground pto0 : programmable timer output md0-md3 : mode selection buz : buzzer clock v pp : programming/verifying power supply pcl : programmable clock remark mft: multifunction timer h mft a/d mode
m pd75p036 4 block diagram basic interval timer timer /counter #0 serial inter- face intbt intt0 intcsi inter- rupt control watch timer a/d con- verter multi- function timer intw intmft ti0/p13 pto0/p20 si/sb1/p03 so/sb0/p02 sck/p01 int0/p10 int1/p11 int2/p12 int4/p00 kr0-kr3/p60-p63 kr4-kr7/p70-p73 an0-an3/p110-p113 an4-an7 buz/p23 av dd av ss av ref av ref+ ppo/p21 mat/p103 maz/p102 mai/p101 mar/p100 pcl/p22 cpu clock clock divider clock output control sub main clock generator stand by control xt1 xt2 x1 x2 v pp v dd v ss reset program counter prom program memory 16256 x 4 bits decode and control bit seq. buffer ram data memory 1024 x 4 bits general reg. bank sp cy alu port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port 10 port 11 p00?03 p10?13 p20?23 p30/md0-p33/md3 p40?43 p50?53 p60?63 p70?73 p80?83 p90?93 p100?103 p110?113 f x /2 n f
m pd75p036 5 contents 1. pin functions ... 6 1.1 port pins ... 6 1.2 non-port pins ... 8 1.3 pin input/output circuits ... 10 1.4 recommended connection of unused pins ... 13 2. memory ... 14 2.1 differences between m pd75p036 and m pd75028/75036 ... 14 2.2 program memory (rom) ... 15 2.3 data memory (ram) ... 17 3. writing and verifying prom (program memory) ... 19 3.1 operation modes for writing/verifying program memory ... 19 3.2 program memory write procedure ... 20 3.3 program memory read procedure ... 21 3.4 erasure ( m pd75p036kg only) ... 22 4. electrical specifications ... 23 5. characteristic curves ... 38 6. package drawings ... 44 7. recommended soldering conditions ... 47 appendix a. development tools ... 48 appendix b. related documents ... 49 h h h h
m pd75p036 6 pin name input/output alternate function 8-bit i/o when reset input/output function circuit type note 1 p00 input int4 4-bit input port (port0). no input b p01 input/output sck internal pull-up resistors can be specified in f - a p02 input/output so/sb0 3-bit units for the p01 to p03 pins by f - b p03 input/output si/sbi software. m - c p10 input int0 with noise elimination function no input b - c p11 int1 4-bit input port (port1). p12 int2 internal pull-up resistors can be specified in p13 ti0 4-bit units by software. p20 input/output pto0 4-bit input/output port (port2). no input e - b p21 ppo internal pull-up resistors can be specified in p22 pcl 4-bit units by software. p23 buz p30 note 2 input/output md0 programmable 4-bit input/output port no input e - b p31 note 2 md1 (port3). p32 note 2 md2 this port can be specified for input/output p33 note 2 md3 in bit units. internal pull-up resistors can be specified in 4-bit units by software. note 2 n-ch open-drain 4-bit input/output port yes input m - a p40-p43 input/output (port4). withstands up to 10 v. data input/output pin for writing and verifying of program memory (prom) (lower 4 bits). note 2 input/output n-ch open-drain 4-bit input/output port input m - a p50-p53 (port5). withstands up to 10 v. data input/output pin for writing and verifying of program memory (prom) (upper 4 bits). 1. pin functions 1.1 port pins (1/2) notes 1 . circles indicate schmitt-triggerred inputs. 2 . can directly drive leds.
m pd75p036 7 pin name input/output alternate function 8-bit i/o when reset input/output function circuit type note 1 p60 input/output kr0 programmable 4-bit input/output port yes input f - a p61 kr1 (port6). p62 kr2 internal pull-up resistors can be specified in p63 kr3 4-bit units by software. p70 input/output kr4 4-bit input/output port (port7). input f - a p71 kr5 internal pull-up resistors can be specified in p72 kr6 4-bit units by software. p73 kr7 p80-p83 input/output 4-bit input/output port (port8). no input e - b internal pull-up resistors can be specified in 4-bit units by software. p90-p93 input/output 4-bit input/output port (port9). input e - d internal pull-up resistors can be specified in 4-bit units by software. p100 input/output mar n-ch open-drain 4-bit input/output port no input m -a p101 mai (port10). p102 maz withstands up to 10 v in open-drain mode. p103 mat p110 input an0 4-bit input/output port (port11). input y p111 an1 p112 an2 p113 an3 1.1 port pins (2/2) note circles indicate schmitt-triggerred inputs.
m pd75p036 8 pin name input/output alternate function 8-bit i/o when reset input/output function circuit type note 1 ti0 input p13 external event pulse input pin to timer/event counter input b - c pto0 input/output p20 timer/event counter output pin input e - b pcl input/output p22 clock output pin input e - b buz input/output p23 fixed frequency output pin (for buzzer or for trimming input e - b the system clock) sck input/output p01 serial clock input/output pin input f - a so/sb0 input/output p02 serial data output pin input f - b serial bus input/output pin si/sb1 input/output p03 serial data output pin input m - c serial bus input/output pin int4 input p00 edge detection vectored interrupt input pin (either input b rising or falling edge detection is effective) int0 input p10 edge detection vectored interrupt input pin (detection input b - c int1 p11 edge can be selected) int2 input p12 edge detection testable input pin (rising edge detection) input b - c kr0-kr3 input/output p60-p63 testable input/output pin (parallel falling edge detection) input f - a kr4-kr7 input/output p70-p73 testable input/output pin (parallel falling edge detection) input f - a mar input/output p100 in integral a/d reverse integration signal output pin input m - a mai input/output p101 converter mode integration signal output pin input m - a maz input/output p102 of mft auto zero signal output pin input m - a mat input/output p103 comparator input pin input m - a ppo input/output p21 in timer mode timer pulse output pin input e - b of mft 1.2 non-port pins (1/2) note circles indicate schmitt-triggerred inputs. remark mft: multifunction timer
m pd75p036 9 1.2 non-port pins (2/2) pin name input/output alternate function when reset input/output function circuit type note 1 an0-an3 input p110-p113 pins only for a/d 8-bit analog input pin. y an4-an7 converter y - a av ref+ input reference voltage input z - a pin (av dd side). av refC input reference voltage input z - a pin (av ss side). av dd positive power supply pin. av ss gnd potential pin. x1, x2 input crystal or ceramic resonator connection for main system clock generation. to use external clock, input the external clock to x1 and its reverse phase to x2. xt1, xt2 input crystal or ceramic resonator connection for subsystem clock generation. to use external clock, input the external clock to xt1 and its reverse phase to xt2. xt1 can be used as a 1-bit input (test) pin. reset input system reset input pin. b md0/md3 input/output p30-p33 mode selection pins in program memory (prom) input e - b write/verify mode. v pp note 2 program voltage application pin in program memory (prom) write/verify mode. at normal operation, connect the pin to v dd directly. in the prom write/verify mode, apply +12.5 v. v dd positive power supply pin. v ss gnd potential pin. notes 1 . circles indicate schmitt trigger inputs. 2 . if the v pp pin is not connected directly to the v dd pin at normal operation, the m pd75p036 does not operate normally.
m pd75p036 10 1.3 pin input/output circuits the following shows a simplified input/output circuit diagram for each pin of the m pd75p036. type a (for type e - b) type d (for type e - b, f - a) type b in v dd v dd p-ch n-ch cmos-level input buffer data output disable out p-ch n-ch push-pull output that can be set in an output high-impedance state (both p-ch and n-ch are off) in schmitt-triggerred input with hysteresis characteristics data output disable type d type a p.u.r. enable v dd p.u.r. p-ch in/out data output disable type d in/out p.u.r. : pull-up resistor p.d.r. : pull-down resistor p.d.r. enable p.d.r. n-ch type a in p.u.r. enable v dd p.u.r. p-ch type b - c type e - b type e - d p.u.r. : pull-up resistor
m pd75p036 11 type f - a type y type m - a type m - c data output disable type d type b p.u.r. enable v dd v dd p-ch p-ch p.u.r. p.u.r. in/out p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor type f - b data output disable p.u.r. enable p.u.r. n-ch p-ch p-ch p-ch n-ch p-ch n-ch output disable (p) output disable (n) v dd in/out type y - a in/out n-ch (+10-v voltage) data output disable middle-voltage input buffer (withstands up to + 10 v) data output disable p.u.r. enable v dd in/out n-ch p.u.r. : pullup resistor in av ss av dd av dd av dd av ss av ss av dd av ss sam- pling c sam- pling c + input enable reference voltage (from serial resistor string voltage tap) reference voltage (from serial resistor string voltage tap) in + input buffer in instruction
m pd75p036 12 av ref+ av ref- reference voltage type z - a
m pd75p036 13 pin name recomended connecting method p00/int4 connect to v ss . p01/sck connect to v ss or v dd . p02/so/sb0 p03/si/sb1 p10/int0-p12/int2 connect to v ss . p13/ti0 p20/pto0 input state: independently connect to v ss or v dd via a p21/ppo resistor. p22/pcl output state: leave open. p23/buz p30/md0-p33/md3 p40-p43 p50-p53 p60/kr0-p63/kr3 p70/kr4-p73/kr7 p80-p83 p90-p93 p100/mar p101/mai p102/maz p103/mat p110/an0-p113/an3 connect to v ss or v dd . an4-an7 av ref+ connect to v ss . av refC av ss av dd connect to v dd . xt1 connect to v ss or v dd . xt2 leave open. v pp connect directly to v dd . 1.4 recommended connection of unused pins h
m pd75p036 14 2. memory 2.1 differences between m pd75p036 and m pd75028/75036 the m pd75p036 is a microcontroller provided by replacing the m pd75028's on-chip mask rom with one-time prom or eprom. capacity of program memory and data memory are different, but cpu function and internal hardware are identical. table 2-1 shows the differences between the m pd75p036 and m pd75028/75036. users should fully consider these differences especially when debugging or producing an application system on an experimental basis by using the prom version and then mass-producing the system using the mask rom version. for details about the cpu function and the internal hardware, refer to m pd75028 user's manual (iem-1280) . table 2-1. differences between m pd75p036 and m pd75028/75036 item m pd75p036 m pd75028 m pd75036 program memory one-time prom/eprom mask rom 0000h-3f7fh 0000h-1f7fh 0000h-3f7fh (16256 x 8 bits) (8064 x 8 bits) (16256 x 8 bits) data memory 000h-3ffh 000h-1ffh 000h-3ffh (1024 x 4 bits) (512 x 4 bits) (1024 x 4 bits) pull-up resistor ports 0-3, 6-8 can be specified by software. ports 4, 5, 10 not provided can be connected by mask option pull-down resistor port 9 can be specified by software. xt1 feedback resistor provided on-chip can be disconnected by mask option supply voltage v dd = 2.7 to 6.0 v pin connection pin 16 (sdip) v pp internally connected pin 25 (qfp) pins 60-63 p33/md3-p30/md0 p33-p30 (sdip) pins 5-8 (qfp) electrical specifications supply current and operating temperature ranges differ between m pd75p036 and m pd75028/75036. for details, refer to the electrical specifications described in data sheet of each model. others noise immunity and noise radiation differ because circuit complexity and mask layout are different. caution the noise immunity and noise radiation differ between the prom and mask rom versions. to replace the prom version with the mask rom version in the course of experimental production to mass production, evaluate your system by using the cs version (not es) of the mask rom version. h
m pd75p036 15 2.2 program memory (rom) 16256 words x 8 bits the program memory is a 16256-word x 8-bit prom and stores programs, table data, etc. the program memory is accessed by referencing the program counter contents. table data can be referenced by executing a table look-up instruction (movt). figure 2-1 shows the address range in which a branch can be taken by branch instructions and subroutine call instructions. a relative branch instruction (br $addr) enables a branch to addresses [pc value C15 to C1, +2 to +16] regardless of block boundaries. program memory addresses are 0000h-3f7fh and the following addresses are assigned to special purposes: (all areas except 0000h or 0001h can be used as normal program memory.) ? addresses 0000h-0001h vector table into which the program start address and mbe setting value when the reset signal is generated are written. processing at reset is started at any desired address. ? addresses 0002h-000dh vector table into which the program start address and mbe setting value when each vectored interrupt is generated are written. interrupt servicing can be started at any desired address. ? addresses 0020h-007fh table area referenced by the geti instruction note . note the geti instruction is provided to execute any 2-byte or 3-byte instruction or two 1-byte instructions as a 1- byte instruction; it is used to reduce the number of program steps.
m pd75p036 16 figure 2-1. program memory map mbe 6 internal reset start address (high-order six bits) internal reset start address (low-order eight bits) intbt/int4 start address (high-order six bits) intbt/int4 start address (low-order eight bits) int1 start address (high-order six bits) int1 start address (low-order eight bits) intcsi start address (high-order six bits) intcsi start address (low-order eight bits) int0 start address (high-order six bits) int0 start address (low-order eight bits) intmft start address (high-order six bits) intmft start address (low-order eight bits) int0 start address (high-order six bits) int0 start address (low-order eight bits) geti instruction reference table 0002h 0004h 0006h 0008h 000ah 000ch 07ffh 0080h 007fh 0020h 0000h 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3f7fh address 7 0 callf ! faddr instruction entry address brcb ! caddr instruction branch address brcb ! caddr instruction branch addresses brcb ! caddr instruction branch addresses brcb ! caddr instruction branch addresses br ! addr instruction branch address call ! addr instruction subroutine entry addres br $ addr instruction relative branch address (?5 to ? and +2 to +16) branch destination address and subroutine entry address to be set by geti instruction 0 mbe 0 mbe 0 mbe 0 mbe 0 mbe 0 mbe 0
m pd75p036 17 2.3 data memory (ram) the data memory consists of a data area and a peripheral hardware area as shown in figure 2-2. the data memory consists of banks, each consisting of 256 words x 4 bits, and the following memory banks can be used: ? memory banks 0-3 (data area) ? memory bank 15 (peripheral hardware area) figure 2-2. data memory map (8 x 4) 256 x 4 256 x 4 256 x 4 128 x 4 not implemented f80h fffh 200h 2ffh 300h 3ffh 1ffh 0ffh 008h 000h general purpose register area 007h 0 1 2 15 data memory memory bank 256 x 4 3 100h data area static ram (1024 x 4) stack area peripheral hardware area
m pd75p036 18 (1) data area the data area consists of static ram and is used to store process data and as stack memory when a (subroutine) or an interrupt is executed. even when cpu operation is stopped in the standby mode, the memory contents can be retained for hours with battery backup, etc. the data area is manipulated by executing memory manipulation instructions. the static ram is mapped each 256 x 4 bits in memory banks 0-3. bank 0 is mapped as a data area; it can also be used as a general purpose register area (000h-007h) and a stack area (000h-0ffh). one address of the static ram consists of four bits; however it can be manipulated in 8-bit units by executing 8-bit memory manipulation instructions and bit-wise by executing bit manipulation instructions. to execute an 8-bit memory manipulation instruction, specify an even address. (a) general purpose register area can be handled by executing general purpose register and memory manipulation instructions. a maximum of eight 4-bit registers can be used. the portions of the eight general purpose registers not used by a program can be used as a data area or stack area. (b) stack area is set by an instruction and can be used as a save area when a subroutine is executed or interrupt servicing is performed. (2) peripheral hardware area the peripheral hardware area is mapped in addresses f80h-fffh of memory bank 15. like the static memory, the peripheral hardware area is handled by executing memory manipulation instructions. however, the bit units in which the peripheral hardware can be manipulated vary depending on the address. addresses in which the peripheral hardware is not mapped do not contain data memory and cannot be accessed.
m pd75p036 19 3. writing and verifying prom (program memory) the program memory incorporated in the m pd75p036 is a 16256 x 8-bit electrically writable prom. the pins as listed in the table given below are used for write and verification of the prom. no address is input; instead, an address is updated by inputting a clock from the x1 pin. pin name function v pp applies voltage when program memory is written/verified (normally, at v dd potential) x1, x2 these pins input clock that updates address when program memory is written/verified. to x2 pin, input x1's signal reverse phase. md0-md3 (p30-p33) these pins select operation mode when program memory is written/verified. p40-p43 (lower 4) these pins input/output 8-bit data when program memory is written/verified. p50-p53 (upper 4) v dd power supply voltage application pin. apply 2.7 to 6.0 v to this pin during normal operation and 6 v when program memory is written/verified. cautions 1. always cover the erasure window of the m pd75p036kg with an opaque film except when the contents of the eprom are erased. 2. the one-time prom version m pd75p036cw/gc is not equipped with a window, and therefore, the contents of the program memory of this model cannot be erased by exposing it to ultraviolet rays. 3.1 operation modes for writing/verifying program memory when +6v is applied to the v dd pin of the m pd75p036 with +12.5v applied to the v pp pin, the m pd75p036 is set in the program memory write/verify mode. in this mode, the following operation modes can be set by using the md0- md3 pins. at this time, all remaining pins are set to the v ss potential with pull-down resistors. operating mode specification operating mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l program memory address 0 clear mode l h h h write mode l l h h verify mode h x h h program inhibit mode h x: l or h
m pd75p036 20 3.2 program memory write procedure the program memory write procedure is as follows. high-speed program memory write is possible. (1) connect the unused pins to v ss via pull-down resistors. the x1 pin must be low. (2) supply 5 v to the v dd and v pp pins. (3) wait for 10 m s. (4) set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) write data in 1 ms write mode. (8) set program inhibit mode. (9) set verify mode. if data has been written connectly, proceed to step (10). if data has not yet been written, repeat steps (7) to (9). (10) write additional data for (the number of times data was written (x) in steps (7) to (9)) times 1 ms. (11) set program inhibit mode. (12) supply a pulse to the x1 pin four times to update the program memory address by 1. (13) repeat steps (7) to (12) to the last address. (14) set program memory address 0 clear mode. (15) change the voltages of v dd and v pp pins to 5 v. (16) turn off the power supply. steps (2) to (12) are illustrated below. v pp v pp v dd v dd +1 v dd v dd data input data output data input write verify additional data write address increment x-time repetition p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) x1
m pd75p036 21 3.3 program memory read procedure the m pd 75p036 program memory contents can be read in the following procedure. read operation should be performed in the verify mode. (1) connect the unused pins to v ss via pull-down resistors. the x1 pin must be low. (2) supply 5 v to the v dd and v pp pins. (3) wait for 10 m s. (4) set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) set verify mode. data of each address is sequentially output each time a clock pulse is input to the x1 pin four times. (8) set program inhibit mode. (9) set program memory address 0 clear mode. (10) change the voltages of v dd and v pp pins to 5 v. (11) turn off the power supply. steps (2) to (9) are illustrated below. v pp v dd v dd +1 v dd v pp v dd data output "l" data output p40-p43 p50-p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) x1
m pd75p036 22 3.4 erasure ( m pd75p036kg only) the contents of the data programmed to the m pd75p036 can be erased by exposing the window to ultraviolet rays. the wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the ultraviolet rays necessary for complete erasure is 15 w?s/cm 2 (= ultraviolet ray intensity x erasure time). when a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mw/cm 2 ) is used, about 15 to 20 minutes is required. cautions 1. the contents of the program memory may be erased if the m pd75p036 is exposed for a long time to direct sunlight or a fluorescent light. to protect the contents from being erased, mask the window with the opaque film. nec attaches quality-tested opaque film to the uv eprom products for shipping. 2. to erase the memory contents, the distance between the ultraviolet ray lamp and the m pd75p036 should be 2.5 cm or less. remark the time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the surface condition (dirt) of the window. h
m pd75p036 23 parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v input voltage v i1 other than ports 4, 5, or 10 C0.3 to v dd +0.3 v v i2 ports 4, 5 and 10 open-drain C0.3 to +11 v output voltage v o C0.3 to v dd +0.3 v output current, high i oh per pin C10 ma all pins C30 ma output current, low i ol note ports 0, 3, 4 and 5 peak value 30 ma per pin r.m.s. value 15 ma other than ports peak value 20 ma 0, 3, 4 and 5 r.m.s. value 5 ma per pin total for ports 0, 3-9, 11 peak value 170 ma r.m.s. value 120 ma total for 0, 2, 10 peak value 30 ma r.m.s. value 20 ma operating ambient temperature t a C40 to +70 c storage temperature t stg C65 to +150 c 4. electrical specifications absolute maximum ratings (t a = 25 c) note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] x duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. capacitance (t a = 25 c, v dd = 0 v) h h parameter symbol test conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf output capacitance c o unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf
m pd75p036 24 main system clock oscillator characteristics (t a = C40 to +70 c, v dd = 2.7 to 6.0 v) resonator recommended parameter test conditions min. typ. max. unit constants ceramic oscillation frequency v dd = oscillation voltage 2.0 5.0 note 3 mhz resonator (f x ) note 1 range oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscilaltion frequency 2.0 4.19 5.0 note 3 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 6.0 v 10 ms time note 2 30 ms external clock x1 input frequency 2.0 5.0 note 3 mhz (f x ) note 1 x1 input high- and 100 250 ns low-level widths (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency are indicated only to express the characteristics of the oscillator. for instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range or the stop mode has been released. 3. when the oscillation frequency is 4.19 mhz < fx 5.0 mhz, do not select pcc = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 m s, falling short of the rated minimum value of 0.95 m s. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. h x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2 pd74hcu04 m
m pd75p036 25 subsystem clock oscillator characteristics (t a = C40 to +70 c, v dd = 2.7 to 6.0 v) resonator recommended parameter test conditions min. typ. max. unit constants crystal oscillation frequency 32 32.768 35 khz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 6.0 v 1.0 2 s time note 2 10 s external clock x1 input frequency 32 100 khz (f x ) note 1 x1 input high-, low-level 5 15 m s widths (t xh , t xl ) notes 1. the oscillation frequency and xt1 input frequency are indicated only to express the characteristics of the oscillator. for instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range. cautions when using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock circuit is influenced by noise more easily than the main system clock oscillation circuit. when using th subsystem clock, therefore, exercise utmost care in wiring the circuit. h xt1 xt2 c3 c4 r v dd x1 x2
m pd75p036 26 parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 ports 2, 3, 8, 9, 11 0.7v dd v dd v v ih2 ports 0, 1, 6, 7, reset 0.8v dd v dd v v ih3 ports 4, 5, 10 open-drain 0.7v dd 10 v v ih4 x1, x2, xt1, xt2 v dd C0.5 v dd v input voltage, low v il1 ports 2 to 5, 8 to 11 0 0.3v dd v v il2 ports 0, 1, 6, 7, reset 0 0.2v dd v v il3 x1, x2, xt1, xt2 0 0.4 v output voltage, high v oh v dd = 4.5 to 6.0 v, i oh = C1 ma v dd C1.0 v i oh = C100 m av dd C0.5 v output voltage, low v ol ports 3, 4, 5 v dd = 4.5 to 6.0 v, 0.4 2.0 v i ol = 15 ma v dd = 4.5 to 6.0 v, i ol = 1.6 ma 0.4 v i ol = 400 m a 0.5 v sb0, 1 open-drain 0.2v dd v pull-up resistor 3 1 k w input leakage current, high i lih1 v i = v dd other than below 3 m a i lih2 x1, x2, xt1, xt2 20 m a i lih3 v i = 9 v ports 4, 5, 10 20 m a (open-drain) input leakage current, low i lil1 v i = 0 v other than below C3 m a i lil2 x1, x2, xt1, xt2 C20 m a input leakage current, high i loh1 v o = v dd 3 m a i loh2 v o = 9 v ports 4, 5, 10 20 m a (open-drain) input leakage current, low i lol v o = 0 v C3 m a internal pull-up resistor r ui ports 0, 1, 2, v dd = 5.0 v 10 %154080k w 3, 6, 7, 8 v dd = 3.0 v 10 % 30 300 k w (except p00) v i = v dd internal pull-down resistor r d port 9 v dd =5.0 v 10 %104070k w v i = v dd v dd = 3.0 v 10 % 10 60 k w dc characteristics (t a = C40 to +70 c, v dd = 2.7 to 6.0 v)
m pd75p036 27 parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 4.19 mhz v dd = 5 v 10% note 3 4.5 14 ma crystal v dd = 3 v 10% note 4 0.9 3 ma i dd2 oscillator note 2 halt v dd = 5 v 10% 700 2100 m a c1 = c2 = 22 pf mode v dd = 3 v 10% 300 900 m a i dd3 32.768 khz operating v dd = 3 v 10% 100 300 m a crystal mode i dd4 oscillator note 5 halt v dd = 3 v 10% 20 60 m a mode i dd5 xt1 = 0 v v dd = 5 v 10% 0.5 20 m a stop mode v dd = 0.1 10 m a 3 v 10% t a = 25?c 0.1 5 m a i dd6 32.768 khz v dd = 3 v 10% note 6 515 m a crystal oscillator stop mode notes 1. currents for the internal pull-up resistor are not included. 2. including when the subsystem clock is operated. 3. high-speed mode operation (when processor clock control register (pcc) is set to 0011). 4. low-speed mode operation (when pcc is set to 0000). 5. when operated with the subsystem clock by setting the system clock control register (scc) to scc3 = 1 and scc0 = 0 to stop the main system clock operation. 6. when subsystem clock is operated by executing stop instruction during main system clock operation.
m pd75p036 28 parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operating on v dd = 4.5 to 6.0 v 0.95 32 m s (minimum instruction execution main system clock 3.8 32 m s time = 1 machine cycle) operating on 114 122 125 m s subsystem clock ti0 input frequency f ti v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz ti0 input high-, low-level widths t tih ,v dd = 4.5 to 6.0 v 0.48 m s t til 1.8 m s interrupt input high-, low-level t inth , int0 note 2 m s widths t intl int1, 2, 4 10 m s kr0 - 7 10 m s reset low-level width t rsl 10 m s ac characteristics (t a = C40 to +70 c, v dd = 2.7 to 6.0 v) notes 1. the cpu clock ( f ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (scc), and processor clock control register (pcc). the figure on the right is cycle time t cy vs. supply voltage v dd characteristics at the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 32 6 5 4 3 2 1 0.5 0123456 operation guaranteed range (during main system clock operation) power supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd m
m pd75p036 29 serial transfer operation two-wire and three-wire serial i/o modes (sck: internal clock output) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level widths t kl1 v dd = 4.5 to 6.0 v (t kcy1 /2)C50 ns t kh1 (t kcy1 /2)C150 ns si setup time (to sck )t sik1 150 ns si hold time (from sck - )t ksi1 400 ns so output delay time t kso1 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns from sck c l = 100 pf note 0 1000 ns h two-wire and three-wire serial i/o modes (sck: external clock input) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-, low-level widths t kl2 v dd = 4.5 to 6.0 v 400 ns t kh2 1600 ns si setup time (to sck )t sik2 100 ns si hold time (from sck - )t ksi2 400 ns so output delay time t kso2 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns from sck c l = 100 pf note 0 1000 ns note r l and c l are load resistance and load capacitance of the so output line. h h h
m pd75p036 30 parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-/low-level widths t kl4 v dd = 4.5 to 6.0 v 400 ns t kh4 1600 ns sb0, 1 setup time (to sck - )t sik4 100 ns sb0, 1 hold time (from sck - )t ksi4 t kcy4 /2 ns sb0, 1 output delay time t kso4 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns from sck c l = 100 pf note 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l are load resistance and load capacitance of the so output line. sbi mode (sck: external clock output (master)) sbi mode (sck: internal clock output (master)) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy3 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-/low-level widths t kl3 v dd = 4.5 to 6.0 v (t kcy3 /2)C50 ns t kh3 (t kcy3 /2)C150 ns sb0, 1 setup time (to sck - )t sik3 150 ns sb0, 1 hold time (from sck - )t ksi3 t kcy3 /2 ns sb0, 1 output delay time t kso3 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns from sck c l = 100 pf note 0 1000 ns sb0, 1 from sck - t ksb t kcy3 ns sck from sb0, 1 t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns
m pd75p036 31 parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit absolute accuracy note 1 2.5 v av ref+ av dd C10 t a 70 ?c 1.5 lsb C40 t a C10 ?c 2.0 lsb conversion time note 2 t conv 168/f x m s sampling time note 3 t samp 44/f x m s analog input voltage v ian av refC av ref+ v analog supply voltage av dd 2.5 v dd v reference input voltage note 4 av ref+ 2.5 v (av ref+ ) C (av refC ) 2.5 av dd v reference input voltage note 4 av refC 2.5 v (av ref+ ) C (av refC ) 0 1.0 v analog input high impedance r an 1000 m w av ref current ai ref 0.35 2.0 ma a/d converter (t a = C40 to +70?c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) notes 1. absolute accuracy from which quantization error ( 1/2 lsb) is removed. 2. time until conversion end (eoc = 1) after conversion start instruction execution (40.1 m s: operation at fx = 4.19 mhz). 3. time until sampling end after conversion start instruction execution (10.5 m s: operation at fx = 4.19 mhz). 4. (av ref+ ) C (ab refC ) should be 2.5 v or more.
m pd75p036 32 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 1/f x t xl t xh v dd - 0.5 v 0.4 v x1 input 1/f xt t xtl t xth v dd - 0.5 v 0.4 v xt1 input 1/f ti t til t tih ti0 ac timing test point (excluding x1 and xt1 inputs) clock timing ti0 timing
m pd75p036 33 t kso1 sck si so input data output data t kcy1 t kh1 t kl1 t sik1 t ksi1 sck t kl2 t kh2 t kcy2 t sik2 t ksi2 sb0,1 t kso2 serial transfer timing three-wire serial i/o mode: two-wire serial i/o mode:
m pd75p036 34 sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t sbh t sbl t ksb sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t ksb int0,1,2,4 kr0 - 7 t intl t inth reset t rsl serial transfer timing bus release signal transfer reset input timing interrupt input timing command signal transfer
m pd75p036 35 parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 2.0 6.0 v data retention supply i dddr v dddr = 2.0 v 0.1 10 m a current note 1 release signal set time t srel 0 m s oscillation stabilization wait t wait released by reset 2 17 /f x ms time note 2 released by interrupt note 3 ms btm3 btm2 btm1 btm0 wait time ( ): f x = 4.19 mhz 0 0 0 2 20 /f x (approx. 250 ms) 0 1 1 2 17 /f x (approx. 31.3 ms) 1 0 1 2 15 /f x (approx. 7.82 ms) 1 1 1 2 13 /f x (approx. 1.95 ms) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel data memory stop mode: low-voltage data retention characteristics (t a = C40 to +70 c) notes 1. does not include current in the internal pull-up resistor 2. the oscillation stabilization wait time is the time during which the cpu is stopped to prevent unstable operation when oscillation is started. 3. depends on the setting of the basic interval timer mode register (btm) as follows: data retention timing (releasing stop mode by reset) data retention timing (standby release signal: releasing stop mode by interrupt)
m pd75p036 36 parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 other than x1 or x2 0.7v dd v dd v v ih2 x1 and x2 v dd C0.5 v dd v input voltage, low v il1 other than x1 or x2 0 0.3v dd v v il2 x1 and x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a output voltage, high v oh i oh = C1 ma v dd C1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , md1 = v ih 30 ma parameter symbol note 1 test conditions min. typ. max. unit address setup time note 2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time note 2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s data output float delay time from md0 - t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initialized program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t mos t ces 2 m s data output delay time from md0 t dv t dv md0 = md1 = v il 1 m s md1 hold time (from md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr 10 m s x1 input high-/low-level width t xh , t xl 0.125 m s x1 input frequency f x 4.19 mhz initial mode set time t i 2 m s md3 setup time (to md1 - )t m3s 2 m s md3 hold time (from md1 )t m3h 2 m s md3 setup time (from md0 )t m3sr when data is read from 2 program memory m s address note 2 to data output delay time t dad t acc when data is read from 2 m s program memory address note 2 to data output hold time t had t oh when data is read from 0 130 ns program memory md3 hold time (from md0 - )t m3hr when data is read from 2 m s program memory data output float delay time from md3 t dfr when data is read from 2 m s program memory h h dc programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) notes 1. these symbols are correspond to m pd27c256a symbols. 2. the internal address signal is incremented by 1 at the rising edge of fourth x1 input. the internal address is not connected to any pin. cautions 1. v pp must not exceed +13.5 v, including the overshoot. 2. apply v dd before v pp and disconnect it after v pp . ac programming characteristics (t a = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v)
m pd75p036 37 v pp v dd v dd + 1 v dd md0 md1 md2 md3 v pp v dd data input data output data input data input t vps t vds t ds t i t dh t dv t df t ds t ah t as t opw t m1r t pw t pcr t m1s t m1h t m3s t m3h t xh t xl t oh t mos x1 p40-p43 p50-p53 t vps t vds t dv t xh t xl t had t dad data output data output t dfr t m3hr t pcr t m3sr t i v pp v dd v dd + 1 v dd md0 md1 md2 md3 v pp v dd x1 p40-p43 p50-p53 program memory write timing program memory read timing h h
m pd75p036 38 5. characteristic curves (reference values) i dd vs v dd (4.19-mhz main system clock, crystal resonator) h 330 k w crystal resonator 32.768 khz v dd 18 pf v dd crystal resonator 4.19 mhz 22 pf 18 pf 22 pf 6 8 4 2 0 0.005 supply current i dd [ma] 0.001 0.05 0.01 0.5 0.1 3.0 1.0 5.0 (t a = 25 ?) x1 x2 xt1 xt2 supply voltage v dd [v] pcc = 0000 main system clock halt mode + 32 khz oscillation subsystem clock halt mode subsystem clock halt mode main system clock stop mode + 32 khz oscillation pcc = 0011 pcc = 0010
m pd75p036 39 i dd vs v dd (2.0-mhz main system clock, crystal resonator) 330 k w crystal resonator 32.768 khz v dd 18 pf v dd crystal resonator 2.0 mhz 22 pf 18 pf 22 pf 6 8 4 2 0 0.005 supply current i dd [ma] 0.001 0.05 0.01 0.5 0.1 3.0 1.0 5.0 (t a = 25 ?) x1 x2 xt1 xt2 supply voltage v dd [v] pcc = 0010 main system clock halt mode + 32 khz oscillation subsystem clock halt mode subsystem clock halt mode main system clock stop mode + 32 khz oscillation pcc = 0000 pcc = 0011
m pd75p036 40 i dd vs v dd (4.19-mhz main system clock, ceramic resonator) 330 k w crystal resonator 32.768 khz v dd 18 pf v dd ceramic resonator 4.19 mhz 30 pf 18 pf 30 pf 6 8 4 2 0 0.005 supply current i dd [ma] 0.001 0.05 0.01 0.5 0.1 3.0 1.0 5.0 (t a = 25 ?) x1 x2 xt1 xt2 supply voltage v dd [v] pcc = 0010 main system clock halt mode + 32 khz oscillation subsystem clock halt mode subsystem clock halt mode main system clock stop mode + 32 khz oscillation pcc = 0011 pcc = 0000
m pd75p036 41 i dd vs v dd (20-mhz main system clock, ceramic resonator) 330 k w crystal resonator 32.768 khz v dd 18 pf v dd ceramic resonator 2.0 mhz 30 pf 18 pf 30 pf 6 8 4 2 0 0.005 supply current i dd [ma] 0.001 0.05 0.01 0.5 0.1 3.0 1.0 5.0 (t a = 25 ?) x1 x2 xt1 xt2 supply voltage v dd [v] pcc = 0010 main system clock halt mode + 32 khz oscillation subsystem clock halt mode subsystem clock halt mode main system clock stop mode + 32 khz oscillation pcc = 0011 pcc = 0000
m pd75p036 42 i dd vs f x i dd vs f x i ol vs v ol (port 0) i ol vs v ol (ports 2, 6 to 10) 3 4 5 2 1 0 1 023 4 6 5 f x [mhz] (v dd = 5 v, t a = 25 ?) i dd [ma] x1 x2 pcc = 0011 pcc = 0010 pcc = 0000 main system clock halt mode 1.0 1.5 2.0 0.5 0 1 023 4 6 5 f x [mhz] (v dd = 3 v, t a = 25 ?) i dd [ma] x1 x2 pcc = 0010 pcc = 0000 main system clock halt mode i ol [ma] (t a = 25?) 40 30 20 10 0 0 12345 v ol [v] v ol [v] v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v 30 20 25 15 10 5 0 01 2345 v dd = 6 v i ol [ma] v dd = 5 v v dd = 6 v v dd = 4 v v dd = 2.7 v v dd = 3 v (t a = 25?)
m pd75p036 43 i ol vs v ol (ports 3 to 5) i ol [ma] (t a = 25?) 40 30 20 10 0 0 12345 v ol [v] v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v v dd = 6 v i oh vs v dd Cv oh i oh [ma] (t a = 25?) 15 5 10 0 0 12345 v dd ?v oh [v] v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2.7 v v dd = 6 v
m pd75p036 44 6. package drawings a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
m pd75p036 45 n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55? p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
m pd75p036 46 64 pin ceramic wqfn j 1 64 z a b t u c d r h s q w k e g f x64kg-80a-1 item millimeters inches a b c 13.8?.25 13.0 12.4 0.543 0.512 0.488 +0.011 ?.010 d 13.8?.25 0.543 e 1.94 0.076 g 2.14 0.084 h 3.56 max. 0.141 max. i 0.51?.1 0.020?.004 j 0.08 0.003 k 0.8 (t.p.) 0.031 (t.p.) q 1.0?.15 0.039?.006 r c 0.3 c 0.012 s 0.9 0.035 t 0.9 0.035 r 1.5 r 0.059 note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. f u u1 6.0 0.236 w 1.0 0.039 z 0.75?.15 0.030 0.10 0.004 +0.011 ?.010 m i +0.006 ?.007 u1 h
m pd75p036 47 7. recommended soldering conditions it is recommended that the m pd75p036 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor devices mounting technology manual" (iei-1207) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 7-1. soldering conditions for surface mount devices m pd75p036gc-ab8: 64-pin plastic qfp (14 x 14 mm) soldering method soldering conditions recommended soldering code wave soldering soldering bath temperature: 260?c max., ws60-162-1 time: 10 seconds max., number of times: 1, maximum number of days: 2 days note , (thereafter, 16 hours of prebaking is required at 125?c), preheating temperature: 120 c max. (package surface temperature). infrared reflow package peak temperature: 230?c, ir30-162-1 time: 30 seconds max. (210?c min.), number of times: 1, maximum number of days: 2 days note (thereafter, 16 hours of prebaking is required at 125?c) vps package peak temperature: 215?c, vp15-162-1 time: 40 seconds max. (200?c min.), number of times: 1, maximum number of days: 2 days note (thereafter, 16 hours of prebaking is required at 125?c) partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin row) note number of days after unpacking the dry pack. storage conditions are 25 c and 65% rh max. caution do not use different soldering methods together (except the partial heating method). table 7-2. soldering conditions for through-hole devices m pd75p036cw: 64-pin plastic shrink dip (750 mils) soldering method soldering conditions wave soldering (pin only) soldering bath temperature: 260?c max., time: 10 seconds max. partial heating pin temperature: 300?c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the lead part and be careful so as not to bring solder into direct contact with the device body.
m pd75p036 48 appendix a. development tools the following development tools are readily available to support development of systems using m pd75p03s: hardware ie-75000-r note 1 in-circuit emulator for 75k series ie-75001-r ie-75000-r-em note 2 emulation board for ie-75000-r and ie-75001-r ep-75028cw-r emulation prove for m pd75p036cw ep-75028gc-r emulation prove for m pd75p036gc. provided with 64-pin conversion socket. ev-9200gc-64 ev-9200g-80 used for m pd75p036gc/75p036kg pg-1500 prom programmer pa-75p036cw prom programmer adapter used for m pd75p036cw. it is connected to pg-1500. pa-75p036gc prom programmer adapter used for m pd75p036gc. it is connected to pg-1500. software ie control program host machine pg-1500 controller ? pc-9800 series (ms-dos tm ver. 3.30 to ver. 5.00a note 3 ) ra75x relocatable ? ibm pc/at tm (refer to document os for ibm pc ) assembler notes 1. for maintenance purpose only 2. not provided with ie-75001-r 3. ver.5.00/5.00a has a task swap function, but this function cannot be used with these software. remark please refer to the 75x series selection guide (if-1027) for information on third party development tools. os for ibm pc the following os are supported for ibm pc. os version pc dos tm ver. 3.1 to ver. 6.3 j6.1/v note to 16.3/v note ms-dos ver. 5.0 to ver. 6.2 5.0/v note to j6.2/v note ibm dos tm j5.02/v note note supported only english mode. caution ver. 5.0 or later has a task swap function, but this function cannot be used with these software. h
m pd75p036 49 appendix b. related documents please use this document in conjunction with the following. related document may be "preliminary." however, in this document, "preliminary" is not indicated. device document h title document number japanese english m pd75p036 data sheet (this document) ic-7914 ic-2967 m pd75028 user's manual ieu-694 ieu-1280 m pd75028 instruction list iem-5511 m pd75028 application note basics iea-689 iea-1277 75x series selection guide if-151 if-1027 title document number japanese english hardware ie-75000-r/ie-75001-r user's manual eeu-846 eeu-1416 ie-75000-r-em user's manual eeu-673 eeu-1294 ep-75028cw-r user's manual eeu-697 eeu-1314 ie-75028gc-r user's manual eeu-692 eeu-1306 pg-1500 user'ss manual eeu-651 eeu-1335 software ra75x assembler package user's manual operation eeu-731 eeu-1346 language eeu-730 eeu-1363 pg-1500 controller user's manual pc-9800 series eeu-704 scheduled (ms-dos) based ibm pc series eeu-5008 eeu-1291 (pc dos) based development tool document
m pd75p036 50 other document caution the contents of the documents listed above are subject to change without prior notice to user's. make sure to use the latest edition when starting design. title number japanese english package manual iei-635 iei-1213 semiconductor device mounting technology manual iei-616 iei-1207 quality grades on nec semiconductor devices iei-620 iei-1209 nec semiconductor device reliability/quality control system iem-5068 electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices mei-603 mei-1202 microcomputer-related product guide third party products mei-604
m pd75p036 51 notes for cmos devices (1) precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. (2) handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input lelvel may be generated due to noise, etc., hence causing mulfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd75p036 m4 94.11 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standatd", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computer, office equipment, communication equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical eqiupment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nucleare reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may prohibited without governmental license. to export or re-export some or all or these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: m pd75p036kg the customer must judge the need for license: m pd75p036cw, 75p036gc-ab8

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